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1. general description the lpc122x extend nxp's 32-bit arm microcontroller continuum and target a wide range of industrial applications in the area s of factory and home automation. benefitting from the arm cortex-m0 thumb instruction set, the lpc122x have up to 50 % higher code density compared to common 8/16-bit microcontroller performing typical tasks. the lpc122x also feature an optimized rom-based divide library for cort ex-m0, which offers several times the arithmetic performance of so ftware-based libraries, as well as highly deterministic cycle time combined with reduced flash code size. the arm cortex-m0 efficiency also helps the lpc122x achieve lower average power for similar applications. the lpc122x operate at cpu frequencies of up to 45 mhz.they offer a wide range of flash memory options, from 32 kb to 128 kb . the small 512-byte page erase of the flash memory brings multiple desi gn benefits, such as finer eeprom emulation, boot-load support from any serial interface and ease of in-field programming with reduced on-chip ram buffer requirements. the peripheral complement of the lpc122x in cludes a 10-bit adc, two comparators with output feedback loop, two uarts, one ssp/spi interface, one i 2 c-bus interface with fast-mode plus features, a windowed watchdog timer, a dma controller, a crc engine, four general purpose timers, a 32-bit rtc, a 1 % internal oscillator for baud rate generation, and up to 55 general purpose i/o (gpio) pins. 2. features and benefits ? processor core ? arm cortex-m0 processor, running at frequencies of up to 45 mhz (one wait state from flash) or 30 mhz (zero wait stat es from flash). the lpc122x have a high score of over 45 in coremark cpu perfor mance benchmark testing, equivalent to 1.51/mhz. ? arm cortex-m0 built-in nested vectored interrupt controller (nvic). ? serial wire debug (swd). ? system tick timer. ? memory ? up to 8 kb sram. ? up to 128 kb on-chip flash programming memory. ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. ? includes rom-based 32-bit integer division routines. ? clock generation unit lpc122x 32-bit arm cortex-m0 microcontrolle r; up to 128 kb flash and 8 kb sram rev. 2 ? 26 august 2011 product data sheet
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 2 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller ? crystal oscillator with an operating range of 1 mhz to 25 mhz. ? 12 mhz internal rc (irc) osc illator trimmed to 1 % accura cy that can optionally be used as a system clock. ? pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from th e system oscillator or the internal rc oscillator. ? clock output function with divider that ca n reflect the system oscillator clock, irc clock, main clock, and watchdog clock. ? real-time clock (rtc). ? digital peripherals ? micro dma controller with 21 channels. ? crc engine. ? two uarts with fractional baud rate generation and internal fifo. one uart with rs-485 and modem support and one standard uart with irda. ? ssp/spi controller with fifo and multi-prot ocol capabilities. ? i 2 c-bus interface supporting full i 2 c-bus specification and fast-mode plus with a data rate of 1 mbit/s wit h multiple address recognition and monitor mode. i 2 c-bus pins have programmable glitch filter. ? up to 55 general purpose i/o (gpio) pins with programmable pull-up resistor, open-drain mode, programmable digital input glitch filter, and programmable input inverter. ? programmable output drive on all gpio pins. four pins support high-current output drivers. ? all gpio pins can be used as edge and level sensitive interrupt sources. ? four general purpose counter/timers with four capture inputs and four match outputs (32-bit timers) or two capture input s and two match outputs (16-bit timers). ? windowed watchdog timer (wwdt); iec-60335 class b certified. ? analog peripherals ? one 8-channel, 10-bit adc. ? two highly flexible analog comparators. comparator outputs can be programmed to trigger a timer match signal or ca n be used to emulate 555 timer behavior. ? power ? three reduced power modes: sleep, deep-sleep, and deep power-down. ? processor wake-up from deep-sleep mode via start logic using 12 port pins. ? processor wake-up from deep-power down and deep-sleep modes via the rtc. ? brownout detect with three separate thresholds each for interrupt and forced reset. ? power-on reset (por). ? integrated pmu (power management unit). ? unique device serial number for identification. ? 3.3 v power supply. ? available as 64-pin and 48-pin lqfp package.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 3 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 3. applications ? emetering ? lighting ? industrial networking ? alarm systems ? white goods 4. ordering information table 1. ordering information type number package name description version lpc1227fbd64/301 lqfp64 lqfp64: plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc1226fbd64/301 lqfp64 lqfp64: plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 LPC1225fbd64/321 lqfp64 lqfp64: plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 LPC1225fbd64/301 lqfp64 lqfp64: plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc1224fbd64/121 lqfp64 lqfp64: plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc1224fbd64/101 lqfp64 lqfp64: plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc1227fbd48/301 lqfp48 lqfp48: plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1226fbd48/301 lqfp48 lqfp48: plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 LPC1225fbd48/321 lqfp48 lqfp48: plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 LPC1225fbd48/301 lqfp48 lqfp48: plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1224fbd48/121 lqfp48 lqfp48: plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1224fbd48/101 lqfp48 lqfp48: plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 4 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 4.1 ordering options table 2. ordering options for lpc122x type number flash total sram uart i 2 c/ fm+ ssp/ spi adc channels gpio package lpc1227 lpc1227fbd64/301 128 kb 8 kb 2 1 1 8 55 lqfp64 lpc1227fbd48/301 128 kb 8 kb 2 1 1 8 39 lqfp48 lpc1226 lpc1226fbd64/301 96 kb 8 kb 2 1 1 8 55 lqfp64 lpc1226fbd48/301 96 kb 8 kb 2 1 1 8 39 lqfp48 LPC1225 LPC1225fbd64/321 80 kb 8 kb 2 1 1 8 55 lqfp64 LPC1225fbd64/301 64 kb 8 kb 2 1 1 8 55 lqfp64 LPC1225fbd48/321 80 kb 8 kb 2 1 1 8 39 lqfp48 LPC1225fbd48/301 64 kb 8 kb 2 1 1 8 39 lqfp48 lpc1224 lpc1224fbd64/121 48 kb 4 kb 2 1 1 8 55 lqfp64 lpc1224fbd64/101 32 kb 4 kb 2 1 1 8 55 lqfp64 lpc1224fbd48/121 48 kb 4 kb 2 1 1 8 39 lqfp48 lpc1224fbd48/101 32 kb 4 kb 2 1 1 8 39 lqfp48
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 5 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 5. block diagram fig 1. lpc122x block diagram arm cortex-m0 test/debug interface micro dma controller system bus clock generation, power control, system functions xtalin xtalout reset swd crc engine lpc122x master 32/48/64/80/ 96/128 kb flash slave 4/8 kb sram slave rom slave slave slave slave 002aaf269 gpio ports windowed wdt ioconfig rtc 32 khz oscillator system control clkout ssp/spi uart0 rs-485 i 2 c 32-bit counter/timer 0 sck ssel miso mosi 4 mat 4 cap sda scl uart1 txd1 txd0 rxd1 rxd0 32-bit counter/timer 1 4 mat 4 cap 16-bit counter/timer 0 2 mat 2 cap 16-bit counter/timer 1 2 mat 2 cap dtr0, dsr0, cts0, dcd0, ri0, rts0 10-bit adc micro dma registers comparator0/1 ad[7:0] acmp0_i[3:0] acmp1_o acmp1_i[3:0] vref_cmp acmp0_o ahb-lite bus ahb-apb bridge high-speed gpio rtcxout rtcxin irc, oscillators por bod clocks and controls grey-shaded blocks represent peripherals with connection to the micro dma controller
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 6 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 6. pinning information 6.1 pinning (1) high-current output driver. remark: for a full listing of all functions for each pin see table 3 . fig 2. pin configuration lqfp64 package lpc122x xtalin r/pio1_0 xtalout r/pio0_31 vref_cmp r/pio0_30 pio0_19 pio0_18 pio0_20 pio0_17 pio0_21 pio0_16 pio0_22 pio0_15 pio0_23 pio0_14 pio0_24 reset/pio0_13 swdio/pio0_25 pio0_12 (1) swclk/pio0_26 pio0_11 pio0_27 (1) pio0_10 pio2_12 pio2_7 pio2_13 pio2_6 pio2_14 pio2_5 pio2_15 pio2_4 pio0_28 (1) v ssio pio0_29 (1) v dd(io) pio0_0 pio2_11 pio0_1 pio2_10 pio0_2 pio2_9 pio0_3 pio2_8 pio0_4 rtcxin pio0_5 rtcxoout pio0_6 v dd(3v3) pio0_7 v ss pio0_8 pio1_6 pio0_9 pio1_5 pio2_0 pio1_4 pio2_1 pio1_3/wakeup pio2_2 pio1_2 pio2_3 r/pio1_1 002aaf554 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 7 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller (1) high-current output driver. remark: for a full listing of all functions for each pin see table 3 . fig 3. pin configuration lqfp48 package lpc122x xtalin r/pio1_0 xtalout r/pio0_31 vref_cmp r/pio0_30 pio0_19 pio0_18 pio0_20 pio0_17 pio0_21 pio0_16 pio0_22 pio0_15 pio0_23 pio0_14 pio0_24 reset/pio0_13 swdio/pio0_25 pio0_12 (1) swclk/pio0_26 pio0_11 pio0_27 (1) pio0_10 pio0_28 (1) v ssio pio0_29 (1) v dd(io) pio0_0 rtcxin pio0_1 rtcxout pio0_2 v dd(3v3) pio0_3 v ss pio0_4 pio1_6 pio0_5 pio1_5 pio0_6 pio1_4 pio0_7 pio1_3/wakeup pio0_8 pio0_9 pio1_2 r/pio1_1 002aaf724 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 8 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 6.2 pin description all pins except the supply pins can have more than one function as shown in ta b l e 3 . the pin function is selected through the pin?s iocon register in the ioconfig block. the multiplexed functions (see ta b l e 4 ) include the counter/timer inputs and outputs, the uart receive, transmit, and control functi ons, and the serial wire debug functions. for each pin, the default function is list ed first together with the pin?s reset state. table 3. lpc122x pin description symbol pin lqfp48 pin lqfp64 start logic input type reset state [1] description pio0_0 to pio0_31 i/o port 0 ? port 0 is a 32-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. pio0_0/rts0 15 19 [2] [3] yes i/o i; pu pio0_0 ? general purpose digital input/output pin. o- rts0 ? request to send output for uart0. pio0_1/rxd0/ ct32b0_cap0/ ct32b0_mat0 16 20 [2] [3] yes i/o i; pu pio0_1 ? general purpose digital input/output pin. i- rxd0 ? receiver input for uart0. i- ct32b0_cap0 ? capture input, channel 0 for 32-bit timer 0. o- ct32b0_mat0 ? match output, channel 0 for 32-bit timer 0. pio0_2/txd0/ ct32b0_cap1/ ct32b0_mat1 17 21 [2] [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. o- txd0 ? transmitter output for uart0. i- ct32b0_cap1 ? capture input, channel 1 for 32-bit timer 0. o- ct32b0_mat1 ? match output, channel 1 for 32-bit timer 0. pio0_3/dtr0 / ct32b0_cap2/ ct32b0_mat2 18 22 [2] [3] yes i/o i; pu pio0_3 ? general purpose digital input/output pin. o- dtr0 ? data terminal ready output for uart0. i- ct32b0_cap2 ? capture input, channel 2 for 32-bit timer 0. o- ct32b0_mat2 ? match output, channel 2 for 32-bit timer 0. pio0_4/dsr0 / ct32b0_cap3/ ct32b0_mat3 19 23 [2] [3] yes i/o i; pu pio0_4 ? general purpose digital input/output pin. i- dsr0 ? data set ready input for uart0. i- ct32b0_cap3 ? capture input, channel 3 for 32-bit timer 0. o- ct32b0_mat3 ? match output, channel 3 for 32-bit timer 0. pio0_5/dcd0 20 24 [2] [3] yes i/o i; pu pio0_5 ? general purpose digital input/output pin. i- dcd0 ? data carrier detect input for uart0. pio0_6/ri0 / ct32b1_cap0/ ct32b1_mat0 21 25 [2] [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. i- ri0 ? ring indicator input for uart0. i- ct32b1_cap0 ? capture input, channel 0 for 32-bit timer 1. o- ct32b1_mat0 ? match output, channel 0 for 32-bit timer 1.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 9 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller pio0_7/cts0 / ct32b1_cap1/ ct32b1_mat1 22 26 [2] [3] yes i/o i; pu pio0_7 ? general purpose digital input/output pin. i- cts0 ? clear to send input for uart0. i- ct32b1_cap1 ? capture input, channel 1 for 32-bit timer 1. o- ct32b1_mat1 ? match output, channel 1 for 32-bit timer 1. pio0_8/rxd1/ ct32b1_cap2/ ct32b1_mat2 23 27 [2] [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i- rxd1 ? receiver input for uart1. i- ct32b1_cap2 ? capture input, channel 2 for 32-bit timer 1. o- ct32b1_mat2 ? match output, channel 2 for 32-bit timer 1. pio0_9/txd1/ ct32b1_cap3/ ct32b1_mat3 24 28 [2] [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. o- txd1 ? transmitter output for uart1. i- ct32b1_cap3 ? capture input, channel 3 for 32-bit timer 1. o- ct32b1_mat3 ? match output, channel 3 for 32-bit timer 1. pio0_10/scl 25 37 [4] yes i/o i; ia pio0_10 ? general purpose digita l input/output pin. i/o - scl ? i 2 c-bus clock input/output. pio0_11/sda/ ct16b0_cap0/ ct16b0_mat0 26 38 [4] yes i/o i; ia pio0_11 ? general purpose digital input/output pin. i/o - sda ? i 2 c-bus data input/output. i- ct16b0_cap0 ? capture input, channel 0 for 16-bit timer 0. o- ct16b0_mat0 ? match output, channel 0 for 16-bit timer 0. pio0_12/clkout/ ct16b0_cap1/ ct16b0_mat1 27 39 [9] no i/o i; pu pio0_12 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. high-current output driver. o- clkout ? clock out pin. i- ct16b0_cap1 ? capture input, channel 1 for 16-bit timer 0. o- ct16b0_mat1 ? match output, channel 1 for 16-bit timer 0. reset /pio0_13 28 40 [5] [3] no i i; pu reset ? external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_13 ? general purpose digi tal input/output pin. pio0_14/sck 29 41 [2] [3] no i/o i; pu pio0_14 ? general purpose digi tal input/output pin. i/o - sck ? serial clock for ssp/spi. pio0_15/ssel/ ct16b1_cap0/ ct16b1_mat0 30 42 [2] [3] no i/o i; pu pio0_15 ? general purpose digi tal input/output pin. i/o - ssel ? slave select for ssp/spi. i- ct16b1_cap0 ? capture input, channel 0 for 16-bit timer 1. o- ct16b1_mat0 ? match output, channel 0 for 16-bit timer 1. pio0_16/miso/ ct16b1_cap1/ ct16b1_mat1 31 43 [2] [3] no i/o i; pu pio0_16 ? general purpose digi tal input/output pin. i/o - miso ? master in slav e out for ssp/spi. i- ct16b1_cap1 ? capture input, channel 1 for 16-bit timer 1. o- ct16b1_mat1 ? match output, channel 1 for 16-bit timer 1. table 3. lpc122x pin description ?continued symbol pin lqfp48 pin lqfp64 start logic input type reset state [1] description
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 10 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller pio0_17/mosi 32 44 [2] [3] no i/o i; pu pio0_17 ? general purpose digi tal input/output pin. i/o - mosi ? master out slave in for ssp/spi. pio0_18/swclk/ ct32b0_cap0/ ct32b0_mat0 33 45 [2] [3] no i/o i; pu pio0_18 ? general purpose digi tal input/output pin. i- swclk ? serial wire clock, alternate location. i- ct32b0_cap0 ? capture input, channel 0 for 32-bit timer 0. o- ct32b0_mat0 ? match output, channel 0 for 32-bit timer 0. pio0_19/acmp0_i0/ ct32b0_cap1/ ct32b0_mat1 44 [6] [7] no i/o i; pu pio0_19 ? general purpose digi tal input/output pin. i- acmp0_i0 ? input 0 for comparator 0. i- ct32b0_cap1 ? capture input, channel 1 for 32-bit timer 0. o- ct32b0_mat1 ? match output, channel 1 for 32-bit timer 0 pio0_20/acmp0_i1/ ct32b0_cap2/ ct32b0_mat2 55 [6] [7] no i/o i; pu pio0_20 ? general purpose digi tal input/output pin. i- acmp0_i1 ? input 1 for comparator 0. i- ct32b0_cap2 ? capture input, channel 2 for 32-bit timer 0. o- ct32b0_mat2 ? match output, channel 2 for 32-bit timer 0. pio0_21/acmp0_i2/ ct32b0_cap3/ ct32b0_mat3 66 [6] [7] no i/o i; pu pio0_21 ? general purpose digi tal input/output pin. i- acmp0_i2 ? input 2 for comparator 0. i- ct32b0_cap3 ? capture input, channel 3 for 32-bit timer 0. o- ct32b0_mat3 ? match output, channel 3 for 32-bit timer 0. pio0_22/acmp0_i3 7 7 [6] [7] no i/o i; pu pio0_22 ? general purpose digi tal input/output pin. i- acmp0_i3 ? input 3 for comparator 0. pio0_23/ acmp1_i0/ ct32b1_cap0/ ct32b1_mat0 88 [6] [7] no i/o i; pu pio0_23 ? general purpose digi tal input/output pin. i- acmp1_i0 ? input 0 for comparator 1. i- ct32b1_cap0 ? capture input, channel 0 for 32-bit timer 1. o- ct32b1_mat0 ? match output, channel 0 for 32-bit timer 1. pio0_24/acmp1_i1/ ct32b1_cap1/ ct32b1_mat1 99 [6] [7] no i/o i; pu pio0_24 ? general purpose digi tal input/output pin. i- acmp1_i1 ? input 1 for comparator 1. i- ct32b1_cap1 ? capture input, channel 1 for 32-bit timer 1. o- ct32b1_mat1 ? match output, channel 1 for 32-bit timer 1. swdio/acmp1_i2/ ct32b1_cap2/ ct32b1_mat2/ pio0_25 10 10 [6] [7] no i/o i; pu swdio ? serial wire debug input/output, default location. i- acmp1_i2 ? input 2 for comparator 1. i- ct32b1_cap2 ? capture input, channel 2 for 32-bit timer 1. o- ct32b1_mat2 ? match output, channel 2 for 32-bit timer 1. i/o - pio0_25 ? general purpose digi tal input/output pin. swclk/acmp1_i3/ ct32b1_cap3/ ct32b1_mat3/ pio0_26 11 11 [6] [7] no i i; pu swclk ? serial wire clock, default location. i- acmp1_i3 ? input 3 for comparator 1. i- ct32b1_cap3 ? capture input, channel 3 or 32-bit timer 1. o- ct32b1_mat3 ? match output, channel 3 for 32-bit timer 1. i/o pio0_26 ? general purpose digi tal input/output pin. table 3. lpc122x pin description ?continued symbol pin lqfp48 pin lqfp64 start logic input type reset state [1] description
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 11 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller pio0_27/acmp0_o 12 12 [9] no i/o i; pu pio0_27 ? general purpose digi tal input/output pin (high-current output driver). o- acmp0_o ? output for comparator 0. pio0_28/acmp1_o/ ct16b0_cap0/ ct16b0_mat0 13 17 [9] no i/o i; pu pio0_28 ? general purpose digi tal input/output pin (high-current output driver). o- acmp1_o ? output for comparator 1. i- ct16b0_cap0 ? capture input, channel 0 for 16-bit timer 0. o- ct16b0_mat0 ? match output, channel 0 for 16-bit timer 0. pio0_29/rosc/ ct16b0_cap1/ ct16b0_mat1 14 18 [9] no i/o i; pu pio0_29 ? general purpose digi tal input/output pin (high-current output driver). i/o - rosc ? relaxation oscillator for 555 timer applications. i- ct16b0_cap1 ? capture input, channel 1 for 16-bit timer 0. o- ct16b0_mat1 ? match output, channel 1 for 16-bit timer 0. r/pio0_30/ad0 34 46 [6] [3] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_30 ? general purpose digi tal input/output pin. i- ad0 ? a/d converter, input 0. r/pio0_31/ad1 35 47 [6] [3] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_31 ? general purpose digi tal input/output pin. i- ad1 ? a/d converter, input 1. pio1_0 to pio1_6 i/o port 1 ? port 1 is a 32-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block. pins pio1_7 th rough pio1_31 are not available. r/pio1_0/ad2 36 48 [6] [3] no o i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. r/pio1_1/ad3 37 49 [6] [3] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block.do not pull this pin low at reset. i/o - pio1_1 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. pio1_2/swdio/ad4 38 50 [6] [3] no i/o i; pu pio1_2 ? general purpose digital input/output pin. i/o - swdio ? serial wire debug input/output, alternate location. i- ad4 ? a/d converter, input 4. pio1_3/ad5/wakeup 39 51 [8] [3] no i/o i; pu pio1_3 ? general purpose digital input/output pin. i- ad5 ? a/d converter, input 5. i- wakeup ? deep power-down mode wake-up pin. pio1_4/ad6 40 52 [6] [3] no i/o i; pu pio1_4 ? general purpose digital input/output pin. i- ad6 ? a/d converter, input 6. table 3. lpc122x pin description ?continued symbol pin lqfp48 pin lqfp64 start logic input type reset state [1] description
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 12 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller pio1_5/ad7/ ct16b1_cap0/ ct16b1_mat0 41 53 [6] [3] no i/o i; pu pio1_5 ? general purpose digital input/output pin. i- ad7 ? a/d converter, input 7. i- ct16b1_cap0 ? capture input, channel 0 for 16-bit timer 1. o- ct16b1_mat0 ? match output, channel 0 for 16-bit timer 1. pio1_6/ ct16b1_cap1/ ct16b1_mat1 42 54 [2] [3] no i/o i; pu pio1_6 ? general purpose digital input/output pin. i- ct16b1_cap1 ? capture input, channel 1 for 16-bit timer 1. o- ct16b1_mat1 ? match output, channel 1 for 16-bit timer 1. pio2_0 to pio2_15 i/o port 2 ? port 2 is a 32-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins depends on the function selected through the ioconfig register block. pins pio 2_16 through pio2_31 are not available. pio2_0/ ct16b0_cap0/ ct16b0_mat0/ rts0 -29 [2] [3] no i/o i; pu pio2_0 ? general purpose digital input/output pin. i- ct16b0_cap0 ? capture input, channel 0 for 16-bit timer 0. o- ct16b0_mat0 ? match output, channel 0 for 16-bit timer 0. o- rts0 ? request to send output for uart0. pio2_1/ ct16b0_cap1/ ct16b0_mat1/rxd0 -30 [2] [3] no i/o i; pu pio2_1 ? general purpose digital input/output pin. i- ct16b0_cap1 ? capture input, channel 1 for 16-bit timer 0. o- ct16b0_mat1 ? match output, channel 1 for 16-bit timer 0. i- rxd0 ? receiver input for uart0. pio2_2/ ct16b1_cap0/ ct16b1_mat0/txd0 -31 [2] [3] no i/o i; pu pio2_2 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input, channel 0 for 16-bit timer 1. o- ct16b1_mat0 ? match output, channel 0 for 16-bit timer 1. o- txd0 ? transmitter output for uart0. pio2_3/ ct16b1_cap1/ ct16b1_mat1/dtr0 -32 [2] [3] no i/o i; pu pio2_3 ? general purpose digital input/output pin. i- ct16b1_cap1 ? capture input, channel 1 for 16-bit timer 1. o- ct16b1_mat1 ? match output, channel 1 for 16-bit timer 1. o- dtr0 ? data terminal ready output for uart0. pio2_4/ ct32b0_cap0/ ct32b0_mat0/cts0 -33 [2] [3] no i/o i; pu pio2_4 ? general purpose digital input/output pin. i- ct32b0_cap0 ? capture input, channel 0 for 32-bit timer 0. o- ct32b0_mat0 ? match output, channel 0 for 32-bit timer 0. i- cts0 ? clear to send input for uart0. pio2_5/ ct32b0_cap1/ ct32b0_mat1/ri0 -34 [2] [3] no i/o i; pu pio2_5 ? general purpose digital input/output pin. i- ct32b0_cap1 ? capture input, channel 1 for 32-bit timer 0. o- ct32b0_mat1 ? match output, channel 1 for 32-bit timer 0. i- ri0 ? ring indicator input for uart0. table 3. lpc122x pin description ?continued symbol pin lqfp48 pin lqfp64 start logic input type reset state [1] description
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 13 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller pio2_6/ ct32b0_cap2/ ct32b0_mat2/dcd0 -35 [2] [3] no i/o i; pu pio2_6 ? general purpose digital input/output pin. i- ct32b0_cap2 ? capture input, channel 2 for 32-bit timer 0. o- ct32b0_mat2 ? match output, channel 2 for 32-bit timer 0. i- dcd0 ? data carrier detect input for uart0. pio2_7/ ct32b0_cap3/ ct32b0_mat3/dsr0 -36 [2] [3] no i/o i; pu pio2_7 ? general purpose digital input/output pin. i- ct32b0_cap3 ? capture input, channel 3 for 32-bit timer 0. o- ct32b0_mat3 ? match output, channel 3 for 32-bit timer 0. i- dsr0 ? data set ready input for uart0. pio2_8/ ct32b1_cap0/ ct32b1_mat0 -59 [2] [3] no i/o i; pu pio2_8 ? general purpose digital input/output pin. i- ct32b1_cap0 ? capture input, channel 0 for 32-bit timer 1. o- ct32b1_mat0 ? match output, channel 0 for 32-bit timer 1. pio2_9/ ct32b1_cap1/ ct32b1_mat1 -60 [2] [3] no i/o i; pu pio2_9 ? general purpose digital input/output pin. i- ct32b1_cap1 ? capture input, channel 1 for 32-bit timer 1. o- ct32b1_mat1 ? match output, channel 1 for 32-bit timer 1. pio2_10/ ct32b1_cap2/ ct32b1_mat2/txd1 -61 [2] [3] no i/o i; pu pio2_10 ? general purpose digi tal input/output pin. i- ct32b1_cap2 ? capture input, channel 2 for 32-bit timer 1. o- ct32b1_mat2 ? match output, channel 2 for 32-bit timer 1. o- txd1 ? transmitter output for uart1. pio2_11/ ct32b1_cap3/ ct32b1_mat3/rxd1 -62 [2] [3] no i/o i; pu pio2_11 ? general purpose digital input/output pin. i- ct32b1_cap3 ? capture input, channel 3 for 32-bit timer 1. o- ct32b1_mat3 ? match output, channel 3 for 32-bit timer 1. i- rxd1 ? receiver input for uart1. pio2_12/rxd1 - 13 [2] [3] no i/o i; pu pio2_12 ? general purpose digi tal input/output pin. i- rxd1 ? receiver input for uart1. pio2_13/txd1 - 14 [2] [3] no i/o i; pu pio2_13 ? general purpose digi tal input/output pin. o- txd1 ? transmitter output for uart1. pio2_14 - 15 [2] [3] no i/o i; pu pio2_14 ? general purpose digi tal input/output pin. pio2_15 - 16 [2] [3] no i/o i; pu pio2_15 ? general purpose digi tal input/output pin. rtcxin 46 58 [10] - i - input to the 32 khz oscillator circuit. rtcxout 45 57 [10] - o - output from the 32 kh z oscillator amplifier. xtalin 1 1 - i - input to the system oscillator circuit and internal clock generator circuits. xtalout 2 2 - o - output from the system oscillator amplifier. vref_cmp 3 3 - i - reference voltage for comparator. table 3. lpc122x pin description ?continued symbol pin lqfp48 pin lqfp64 start logic input type reset state [1] description
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 14 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = output; pu = internal pull-up enabled; ia = inactive, no pull-up/dow n enabled. [2] 3.3 v tolerant, digital i/o pin; default: pull-up enabled, no hysteresis. [3] if set to output, this normal-drive pin is in low mode by default. [4] i 2 c-bus pins; 5 v tolerant; open-drain; de fault: no pull-up/pull-down; no hysteresis. [5] 3.3 v tolerant, digital i/o pin with reset function; default: pull-up enabled, no hysteresis. an external pull-up resistor is required on this pin for the deep power-down mode. [6] 3.3 v tolerant, digital i/o pin with analog function; default: pull-up enabled, no hysteresis. [7] if set to output, this normal-drive pin is in high mode by default. [8] 3.3 v tolerant, digital i/o pin wi th analog function and wakeup function; default: pull-up enabled, no hysteresis. [9] 3.3 v tolerant, high-drive digital i/o pin; default: pull-up enabled, no hysteresis. [10] if the rtc is not used, rtcxin and rtcxout can be left floating. to enable a peripheral function, find the corresp onding port pin, or select a port pin if the function is multiplexed, and program the port pin?s ioconfig register to enable that function. the primary swd functions and reset are the default functions on their pins after reset. v dd(io) 47 63 - i - input/output supply voltage. v dd(3v3) 44 56 - i - 3.3 v supply voltage to the internal regulator and the adc. also used as the adc reference voltage. v ssio 48 64 - i - ground. v ss 43 55 - i - ground. table 3. lpc122x pin description ?continued symbol pin lqfp48 pin lqfp64 start logic input type reset state [1] description table 4. pin multiplexing peripheral function type available on ports: analog comparators rosc i/o pio0_29 - - acmp0_i0 i pio0_19 - - acmp0_i1 i pio0_20 - - acmp0_i2 i pio0_21 - - acmp0_i3 i pio0_22 - - acmp0_o o pio0_27 - - acmp1_i0 i pio0_23 - - acmp1_i1 i pio0_24 - - acmp1_i2 i pio0_25 - - acmp1_i3 i pio0_26 - - acmp1_o o pio0_28 - -
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 15 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller adc ad0 i pio0_30 - - ad1 i pio0_31 - - ad2 i pio1_0 - - ad3 i pio1_1 - - ad4 i pio1_2 - - ad5 i pio1_3 - - ad6 i pio1_4 - - ad7 i pio1_5 - - ct16b0 ct16b0_cap0 i pio0_11 pio0_28 pio2_0 ct16b0_cap1 i pio0_12 pio0_29 pio2_1 ct16b0_mat0 o pio0_11 pio0_28 pio2_0 ct16b0_mat1 o pio0_12 pio0_29 pio2_1 ct16b1 ct16b1_cap0 i pio0_15 pio1_5 pio2_2 ct16b1_cap1 i pio0_16 pio1_6 pio2_3 ct16b1_mat0 o pio0_15 pio1_5 pio2_2 ct16b1_mat1 o pio0_16 pio1_6 pio2_3 ct32b0 ct32b0_cap0 i pio0_1 pio0_18 pio2_4 ct32b0_cap1 i pio0_2 pio0_19 pio2_5 ct32b0_cap2 i pio0_3 pio0_20 pio2_6 ct32b0_cap3 i pio0_4 pio0_21 pio2_7 ct32b0_mat0 o pio0_1 pio0_18 pio2_4 ct32b0_mat1 o pio0_2 pio0_19 pio2_5 ct32b0_mat2 o pio0_3 pio0_20 pio2_6 ct32b0_mat3 o pio0_4 pio0_21 pio2_7 ct32b1 ct32b1_cap0 i pio0_6 pio0_23 pio2_8 ct32b1_cap1 i pio0_7 pio0_24 pio2_9 ct32b1_cap2 i pio0_8 pio0_25 pio2_10 ct32b1_cap3 i pio0_9 pio0_26 pio2_11 ct32b1_mat0 o pio0_6 pio0_23 pio2_8 ct32b1_mat1 o pio0_7 pio0_24 pio2_9 ct32b1_mat2 o pio0_8 pio0_25 pio2_10 ct32b1_mat3 o pio0_9 pio0_26 pio2_11 uart0 rxd0 i pio0_1 pio2_1 - txd0 o pio0_2 pio2_2 - cts0 i pio0_7 pio2_4 - dcd0 i pio0_5 pio2_6 - dsr0 i pio0_4 pio2_7 - dtr0 o pio0_3 pio2_3 - ri0 i pio0_6 pio2_5 - rts0 o pio0_0 pio2_0 - table 4. pin multiplexing peripheral function type available on ports:
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 16 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller [1] after reset, the swd functions are se lected by default on pins pio0_26 and pio0_25. 7. functional description 7.1 arm cortex-m0 processor the arm cortex-m0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.1.1 system tick timer the arm cortex-m0 includes a system tick time r (systick) that is in tended to generate a dedicated systick exception at a 10 ms interval. 7.2 on-chip flash program memory the lpc122x contain up to 128 kb of on-chip flash memory. 7.3 on-chip sram the lpc122x contain a total of up to 8 kb on-chip static ram memory. 7.4 memory map the lpc122x incorporates several distinct memory regions, shown in the following figures. figure 4 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb peripheral area is 2 megabyte in si ze, and is divided to allow for up to 128 peripherals. the apb peripheral ar ea is 512 kb in size and is divided to allow for up to 32 peripherals. each peripheral of either type is allocated 16 kilobytes of space. this allows simplifying the address decoding for each peripheral. uart1 rxd1 i pio0_8 pio2_11 pio2_12 txd1 o pio0_9 pio2_10 pio2_13 ssp/spi sck i/o pio0_14 - - miso i/o pio0_16 - - mosi i/o pio0_17 - - ssel i/o pio0_15 - - i2c scl i/o pio0_10 - - sda i/o pio0_11 - - swd swclk [1] i pio0_18 pio0_26 - swdio [1] i/o pio0_25 pio1_2 - reset reset i pio0_13 - - clockout pin clkout o pio0_12 - - table 4. pin multiplexing peripheral function type available on ports:
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 17 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 7.5 nested vectored inte rrupt controller (nvic) the nested vectored in terrupt controller (nvic) is an integral part of the cortex-m0. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. 7.5.1 features ? controls system exceptions and peripheral interrupts. fig 4. lpc122x memory map 0x5000 0000 0x5001 0000 0x5002 0000 ahb peripherals 3 - 6 reserved gpio pio1 1 0x5003 0000 gpio pio2 2 0x5007 0000 0x5008 0000 crc 7 gpio pio0 0 apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wdt 32-bit counter/timer 0 32-bit counter/timer 1 adc uart0 uart1 pmu i 2 c-bus 9 - 13 reserved 22 - 31 reserved 0 1 2 3 4 5 6 7 8 16 15 14 17 18 reserved reserved 0x0000 0000 0 gb 4 gb 1 gb 0x0000 c000 0x0000 8000 0x1000 1000 0x1fff 0000 0x1fff 2000 0x4000 0000 0x4008 0000 0x5000 0000 0x5008 0000 0xffff ffff reserved reserved apb peripherals ahb peripherals 4 kb sram (lpc1224) 0x1000 2000 8 kb sram (LPC1225/6/7) 0x1ffc 0000 reserved 0x1ffc 4000 16 kb nxp library rom 0x1ffe 0000 reserved 0x1ffe 2000 8 kb custom rom reserved 0x1000 0000 lpc122x 48 kb on-chip flash (lpc1224/121) 32 kb on-chip flash (lpc1224/101) 0x0001 0000 64 kb on-chip flash (LPC1225/301) 0x0001 4000 80 kb on-chip flash (LPC1225/321) 0x0001 8000 96 kb on-chip flash (lpc1226/301) 0x0002 0000 128 kb on-chip flash (lpc1227/301) 8 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors reserved ssp 16-bit counter/timer 1 16-bit counter/timer 0 ioconfig system control 0x4005 0000 19 micro dma registers 0x4005 4000 20 rtc 0x4005 8000 21 comparator 0/1 reserved 002aaf270 0xe000 0000 0xe010 0000 private peripheral bus
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 18 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller ? in the lpc122x, the nvic supports 32 vectored interrupts. in addition, up to 12 of the individual gpio inputs are nvic-vector capable. ? four programmable interrupt priority levels with hardware prio rity level masking. ? software interr upt generation. ? non-maskable interrupt (nmi) can be programmed to use any of the peripheral interrupts. the nmi is not available on an external pin. 7.5.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. any gpio pin (total of up to 55 pins) regardless of the selected function, can be programmed to generate an inte rrupt on a level, a rising ed ge or falling edge, or both. 7.6 ioconfig block the ioconfig block allows sele cted pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activi ty of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.6.1 features ? programmable pull-up resistor. ? programmable digital glitch filter. ? programmable input inverter. ? programmable drive current. ? programmable open-drain mode. 7.7 micro dma controller the micro dma controller enables memory-to-memory, memory-to-peripheral, and peripheral-to-memory data transfers. the supported peripherals are: uart0 (transmit and receive), uart1 (transmit and receive), ssp/spi (transmi t and receive), adc, rtc, 32-bit counter/timer 0 (match output channels 0 and 1), 32-bit counter/timer 1 (match output channels 0 and 1), 16-bit counter/timer 0 (match output channel 0), 16-bit counter/timer 1 (match output channel 0), comp arator 0, comparator 1, gpio0 to gpio2. 7.7.1 features ? single ahb-lite master for transferring data using a 32-bit address bus and 32-bit data bus. ? 21 dma channels. ? handshake signals and priority level programmable for each channel. ? each priority level arbitrates using a fixed priority that is determined by the dma channel number.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 19 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller ? supports memory-to-memory, memory-to- peripheral, and peripheral-to-memory transfers. ? supports multiple dma cycle types and multiple dma transfer widths. ? performs all dma transfers using the single ahb-lite burst type. 7.8 crc engine the cyclic redundancy check (crc) engi ne with programmable polynomial settings supports several crc standards commonl y used. to save system power and bus bandwidth, the crc engine supports dma transfers. 7.8.1 features ? supports three common polynomials crc-ccitt, crc-16, and crc-32. ? crc-ccitt: x 16 + x 12 + x 5 + 1 ? crc-16: x 16 + x 15 + x 2 + 1 ? crc-32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? bit order reverse and 1?s complement programmable setting for input data and crc sum. ? programmable seed number setting. ? supports cpu programmed i/o or dma back-to-back transfer. ? accept any size of data width per write: 8, 16 or 32-bit. ? 8-bit write: 1-cycle operation ? 16-bit write: 2-cycle operation (8-bit ? 2-cycle) ? 32-bit write: 4-cycle operation (8-bit ? 4-cycle) 7.9 fast general purpose parallel i/o device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically conf igured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back as well as the current state of the port pins. 7.9.1 features ? bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. ? direction control of individual bits. ? all i/o default to inputs after reset. 7.10 uarts the lpc122x contains two uarts. uart0 supports full modem control and rs-485/9-bit mode and allows both software address detection and automatic hardware address detection using 9-bit mode. the uarts include a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 20 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 7.10.1 features ? 16-byte receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? auto-baud capabilities and fi fo control mechanism that enables software flow control implementation. ? support for rs-485/9-bit mode (uart0). ? support for modem control (uart0). 7.11 ssp/spi serial i/o controller the lpc122x contain one ssp/spi controller. the ssp/spi controller is capable of operation on a ssp, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. the ssp supports full duplex transfers, wi th frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.11.1 features ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame 7.12 i 2 c-bus serial i/o controller the lpc122x contain one i 2 c-bus controller. the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 7.12.1 features ? the i 2 c-interface is a standard i 2 c-compliant bus interface with open-drain pins and supports i 2 c fast-mode plus with bit rates of up to 1 mbit/s. ? programmable digital glitch filter providing a 60 ns to 1 ? s input filter. ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 21 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? the i 2 c-bus controller supports multiple address recognition and a bus monitor mode. 7.13 10-bit adc the lpc122x contains one adc. it is a sing le 10-bit successive approximation adc with eight channels. 7.13.1 features ? 10-bit successive approximation adc. ? input multiplexing among 8 pins. ? power-down mode. ? measurement range 0 v to v dd(3v3) . ? 10-bit conversion time of 257 khz. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of in put pin or counter/timer match signal. ? individual result registers for each adc channel to reduce interrupt overhead. 7.14 comparator block the comparator block consists of two analog comparators. 7.14.1 features ? up to six selectable exter nal sources per comparator; fully configurable on either positive or negative comparator input channels. ? bod 0.9 v internal reference voltage selectable on both comparators; configurable on either positive or negative comparator input channels. ? 32-stage voltage ladder internal reference voltage selectable on both comparators; configurable on either positive or negative comparator input channels. ? voltage ladder source voltage is selectable from an external pin or an internal 3.3 v voltage rail if external powe r source is not available. ? voltage ladder can be separa tely powered down for applic ations only requiring the comparator function. ? relaxation oscillator circui try output for a fe edback 555-style timer application. ? common interrupt connected to nvic. ? comparator outputs selectable as synchronous or asynchronous.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 22 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller ? comparator outputs connect to two timers, allowing for the recording of comparison event time stamps. 7.15 general purpose externa l event counter/timers the lpc122x includes two 32-bit counter/timers and two 16-bit counter/timers. the counter/timer is designed to count cycles of the system derived clock. it can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. each counter /timer also includes up to four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.15.1 features ? a 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. ? counter or timer operation. ? up to four capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? four match registers per timer that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? the timer and prescaler may be configured to be cleared on a designated capture event. this feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capt uring the timer value on the trailing edge. ? supports timed dma requests. 7.16 windowed watc hdog timer (wwdt) the purpose of the watchdog is to reset the microcontroller within a windowed amount of time if it enters an erroneous state. when enabl ed, the watchdog w ill generate a system reset if the user program fails to ?feed? (o r reload) the watchdog within a predetermined amount of time. 7.16.1 features ? internally resets chip if not period ically reloaded. ? debug mode. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? safe operation: can be locked by software to be always on. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 23 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be selected from the in ternal rc oscillator (irc) or the watchdog oscillator. this gives a wide range of potential timing choices of watchdog operation under different power redu ction conditions. it also provides the ability to run the wdt from an entirely internal source that is not dependent on an external crystal and its associated comp onents and wiring for increased reliability. 7.17 real-time clock (rtc) the rtc provides a basic alarm function or ca n be used as a long time base counter. the rtc generates an interrupt after counting for a programmed number of cycles of the rtc clock input. 7.17.1 features ? uses dedicated 32 khz ul tra low-power oscillator. ? selectable clock inputs: rtc oscillator (1 hz , delayed 1 hz, or 1 khz clock) or main clock with programmable clock divider. ? 32-bit counter. ? programmable 32-bit match/compare register. ? software maskable interrupt when counter and compare registers are identical. ? generates wake-up from deep-sleep and deep power-down modes. 7.18 clocking and power control 7.18.1 crystal oscillators the lpc122x include four inde pendent oscillators. these are the system oscillator, the internal rc oscillator (irc), the rtc 32 kh z oscillator (for the rtc only), and the watchdog oscillator. except for the rtc oscill ator, each oscillator can be used for more than one purpose as required in a particular application. following reset, the lpc122x will operate from th e internal rc oscillato r until switched by software. this allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. see figure 5 for an overview of the lpc122x clock generation.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 24 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 7.18.1.1 internal rc oscillator the irc may be used as the clock source for th e wdt, and/or as the clock that drives the pll and subsequently the cpu. the nominal irc frequency is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. upon power-up or any chip reset, the lpc122x use the irc as the clock source. software may later switch to one of the other available clock sources. 7.18.1.2 system oscillator the system oscillator can be used as the clock source for the cpu, with or without using the pll. fig 5. lpc122x clocking generation block diagram system pll watchdog oscillator irc oscillator irc oscillator irc oscillator watchdog oscillator system oscillator mainclksel (main clock select) syspllclksel clock divider ahb clock 0 (system) clock divider peripheral clocks (ssp, uart0, uart1) rtc wwdt watchdog oscillator irc oscillator system oscillator clock divider clkout pin clkoutuen (clkout clock update enable) rtc oscillator 1 khz clock rtc oscillator 1 hz clock rtc oscillator 1 hz delayed clock rtcoscctrl wdclksel (wwdt clock select) main clock system clock 3 clock divider sysahbclkctrl[1:31] (ahb clock enable) ahb clocks 1 to 31 (memories and peripherals) 31 002aaf271 clock divider peripheral clocks (ioconfig glitch filter) 7
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 25 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller the system oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. the arm processor clock frequency is referred to as cclk elsewhere in this document. 7.18.1.3 watchdog oscillator the watchdog oscillator can be used as a clock source that directly drives the cpu, the watchdog timer, or the clkout pin. the watchdog oscillator nominal frequency is programmable between 7.8 khz and 1.7 mhz. th e frequency spread over processing and temperature is ? 40 %. 7.18.2 system pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is provid ing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. the pll output frequency must be lower than 100 mhz. since th e minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 ? s. 7.18.3 clock output the lpc122x features a clock output function that routes the irc oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.18.4 wake-up process the lpc122x begin operation at power-up and when awakened from deep power-down mode by using the 12 mhz irc os cillator as the cloc k source. this allo ws chip operation to resume quickly. if the main oscillator or the pll is neede d by the applicat ion, software will need to enable these features and wait for them to st abilize before they are used as a clock source. 7.18.5 power control the lpc122x support a variety of power control features. there are three special modes of processor power reduction: sleep mode, deep-sleep mode, and deep power-down mode. the cpu clock rate may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power versus processing speed based on application requirements. in addition, a register is provided for shutti ng down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required fo r the application. selected peripherals have their own clock divider which prov ides even better power control. 7.18.5.1 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 26 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.18.5.2 deep-sleep mode in deep-sleep mode, the chip is in sleep mode, and in addition all analog blocks are shut down. as an exception, the user has the opt ion to keep the watchdog oscillator and the bod circuit running for self-timed wake-up and bod protection. deep-sleep mode allows for additional power savings. the gpio pins pio0_0 to pio0_11 (up to 12 pins total) and the rtc match interrupt can serve as a wake-up input to the start logic to wake up the chip from deep-sleep mode. unless the watchdog oscillator is selected to run in deep-s leep mode, the clock source should be switched to irc before entering deep-sleep mode, because the irc can be switched on and off glitch-free. 7.18.5.3 deep power-down mode in deep power-down mode, power is shut off to the entire chip with the exception of the real time clock, the four general-purpose re gisters, and the wakeup pin. the lpc122x can wake up from deep power-down mode via the wakeup pin or the rtc match interrupt. when entering deep power-down mode, an external pull-up resistor is required on the wakeup pin to hold it high. the reset pin must also be held high to prevent it from floating while in deep power-down mode. 7.19 system control 7.19.1 start logic the start logic connects external pins to corresponding interrupts in the nvic. each pin shown in ta b l e 3 as input to the start logic has an individual interrupt in the nvic interrupt vector table. the start logic pins can serve as external interrupt pins when the chip is running. in addition, an input signal on the start logic pins can wake up the chip from deep-sleep mode when all clocks are shut down. the start logic must be configured in the system configuration block and in the nvic before being used. 7.19.2 reset reset has four sources on the lpc122x: the reset pin, the watchdog reset, power-on reset (por), and the brownout detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the irc an d initializes the flash controller. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 27 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller an external pull-up resistor is required on the reset pin if deep power-down mode is used. 7.19.3 brownout detection the lpc122x includes four levels for monitoring the voltage on the v dd(3v3) pin. if this voltage falls below one of the four selected levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for inte rrupt in the interrupt enable register in the nvic in order to cause a cpu in terrupt; if not, software can monitor the signal by reading a dedicated status register. an additional threshold level can be selected to cause a forced reset of the chip. 7.19.4 code security (code read protection - crp) this feature of the lpc122x allows user to enab le different levels of security in the system so that access to the on-chip flash and use of the swd and isp can be restricted. when needed, crp is invoked by programming a specif ic pattern into a dedicated flash location. iap commands are not affected by the crp. there are three levels of code read protection: 1. crp1 disables access to chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of t he isp commands. this mode is useful when crp is required and flash field updates are needed but all sectors can not be erased. 2. crp2 disables access to chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an applicatio n with level crp3 selected fully disables any access to chip via the swd pins and the isp. this mode effect ively disables isp ov erride using pio0_12 pin, too. it is up to the user?s applicat ion to provide (if needed) flash update mechanism using iap calls or call reinvoke isp command to enable flash update via uart0. in addition to the three crp levels, sampli ng of pin pio0_12 for valid user code can be disabled. 7.19.5 apb interface the apb peripherals are located on one apb bus. 7.19.6 ahb-lite the ahb-lite connects the cpu bus of the ar m cortex-m0 to the flash memory, the main static ram, and the boot rom. 7.19.7 external interrupt inputs all gpio pins can be level or edge sensitive interrupt inputs. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 28 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 7.20 emulation and debugging debug functions are integrated into the arm cortex-m0. serial wire debug is supported. 7.21 integer division routines the lpc122x contain performance-optimized int eger division routines with support for up to 32-bit width in the numerator and denominator. routines for signed and unsigned division and division with remainder are av ailable. the integer division routines are rom-based to reduce code-size.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 29 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] the peak current is limited to 25 times the corresponding maximum current. [4] dependent on package type. [5] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) 3.0 3.6 v v dd(io) input/output supply voltage 3.0 3.6 v v i input voltage on all digital pins [2] ? 0.5 +3.6 v on pins pio0_10 and pio0_11 (i 2 c-bus pins) 05.5v i dd supply current per supply pin [3] - 100 ma i ss ground current per ground pin [3] - 100 ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ? c - 100 ma t stg storage temperature [4] ? 65 +150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1 . 5w v esd electrostatic discharge voltage human body model; all pins [5] ? 8000 +8000 v
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 30 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 9. thermal characteristics 9.1 thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. t j t amb p d r th j a ? ?? ? ?? += table 6. thermal characteristics v dd = 3.0 v to 3.6 v; t amb = ? ? ? symbol parameter conditions min typ max unit r th(j-a) thermal resistance from junction to ambient jedec test board; no air flow lqfp64 package - 61 - ? c/w lqfp48 package 86 - ? c/w r th(j-c) thermal resistance from junction to case jedec test board lqfp64 package - 19 - ? c/w lqfp48 package 36 - ? c/w t j(max) maximum junction temperature --150 ? c
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 31 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 10. static characteristics table 7. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd(io) input/output supply voltage on pin v dd(io) 3.0 3.3 3.6 v v dd(3v3) supply voltage (3.3 v) 3.0 3.3 3.6 v i dd supply current active mode; v dd(3v3) =3.3v; t amb =25 ? c; code while(1){} executed from flash all peripherals disabled: cclk = 12 mhz - 4.6 - ma cclk = 24 mhz - 9 - ma cclk = 33 mhz - 12.2 - ma all peripherals enabled: cclk = 12 mhz - 6.6 - ma cclk = 24 mhz - 10.9 - ma cclk = 33 mhz - 14.1 - ma sleep mode; v dd(3v3) = 3.3 v; t amb =25 ?c; all peripherals disabled cclk = 12 mhz - 1.8 - ma cclk = 24 mhz - 3.3 - ma cclk = 33 mhz - 4.4 - ma deep-sleep mode; v dd(3v3) = 3.3 v; t amb =25 ?c -30- ? a deep power-down mode; v dd(3v3) = 3.3 v; t amb =25 ?c - 720 - na normal-drive output pins (standard port pins, reset ) i il low-level input current v i =0v; - - 100 na i ih high-level input current v i =v dd(io) ; - - 100 na i oz off-state output current v o =0v; v o =v dd(io) ; - - 100 na v i input voltage pin configured to provide a digital function [2] [3] [4] 0- v dd(io) v v o output voltage output active 0 - v dd(io) v v ih high-level input voltage 0.7v dd(io) --v
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 32 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller v il low-level input voltage --0.3v dd(i o) v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage low mode; i oh = ? 2 ma v dd(io) ? 0.4 --v high mode; i oh = ? 4 ma v dd(io) ? 0.4 --v v ol low-level output voltage low mode; i ol =2 ma - - 0.4 v high mode; i ol = 4 ma 0.4 i oh high-level output current low mode; v oh = v dd(io) ? 0.4 v ? 2- -ma high mode; v oh = v dd(io) ? 0.4 v ? 4- -ma i ol low-level output current low mode; v ol =0.4v 2 - - ma high mode; v ol =0.4v 4 - - ma i ohs high-level short-circuit output current v oh =0v [5] -- ? 45 ma i ols low-level short-circuit output current v ol =v dda [5] --5 0m a i pu pull-up current v i =0v ? 50 ? 80 ? 100 ? a high-drive output pins (pio0_ 27, pio0_28, pio0_29, pio0_12) i il low-level input current v i =0v; - - 100 na i ih high-level input current v i =v dd(io) ; - - 100 na i oz off-state output current v o =0v; v o =v dd(io) ; - - 100 na v i input voltage pin configured to provide a digital function [2] [3] [4] 0- v dd(io) v v o output voltage output active 0 - v dd(io) v v ih high-level input voltage 0.7v dd(io) --v v il low-level input voltage - - 0.3v dd(io) -- v hys hysteresis voltage - - v v oh high-level output voltage low mode; i oh = ? 20 ma v dd(io) ? 0.7 --v high mode; i oh = ? 28 ma v dd(io) ? 0.7 --v v ol low-level output voltage low mode; i ol = 12 ma - - 0.4 v high mode; i ol = 18 ma - - 0.4 v table 7. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 33 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] including voltage on outputs in 3-state mode. [3] v dd(3v3) and v dd(io) supply voltages must be present. [4] 3-state outputs go into 3-state mode when v dd(io) is grounded. [5] allowed as long as the current limit does not exceed the maximum current allowed by the device. [6] to v ss . i oh high-level output current low mode; v oh = v dd(io) ? 0.7 20 - - ma high mode; v oh = v dd(io) ? 0.7 28 - - ma i ol low-level output current v ol =0.4v low mode 12 - - ma high mode 18 - - ma i ols low-level short-circuit output current v ol =v dd [5] -- m a i pu pull-up current v i =0v ? 50 ? 80 ? 100 ? a i 2 c-bus pins (pio0_10 and pio0_11) v ih high-level input voltage 0.7v dd(io) --v v il low-level input voltage --0.3v dd(i o) v v hys hysteresis voltage - 0.05v dd(io) -v v ol low-level output voltage i ols =20 ma - - 0.4 v i li input leakage current v i =v dd(io) [6] -24 ? a v i =5v - 10 22 ? a c i capacitance for each i/o pin on pins pio0_10 and pio0_11 --8pf oscillator pins v i(xtal) crystal input voltage see section 12.1 01 . 81 . 9 5v v o(xtal) crystal output voltage 0 1.8 1.95 v table 7. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 34 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 10.1 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code is executed. me asured on a typical sample at t amb =25 ? c and v dd(3v3) = 3.3 v. 10.2 power consumption power measurements in active, sleep, and deep-sleep modes were performed under the following conditions (see lpc122x user manual ): ? active mode: all gpio pins set to input with external pull-up resistors. ? sleep and deep-sleep modes: all gpio pins set to output driving low. ? deep power-down mode: all gpio pins set to input with external pull-up resistors. table 8. peripheral power consumption peripheral typical current consumption i dd in ma frequency independent 24 mhz 12 mhz system oscillator + pll irc + pll system oscillator irc irc 0.29 - - - - pll (pll output frequency = 24 mhz) 1.87 - - - - wdosc (wdosc output frequency = 500 khz) 0.25 - - - - bod 0.06 - - - - analog comparator 0/1 - 0.05 0.05 0.03 0.02 adc - 1.86 1.85 1.61 1.61 crc engine - 0.04 0.04 0.02 0.02 16-bit timer 0 (ct16b 0) - 0.09 0.09 0.04 0.04 16-bit timer 1 (ct16b 1) - 0.09 0.09 0.04 0.04 32-bit timer 0 (ct32b 0) - 0.08 0.08 0.04 0.04 32-bit timer 1 (ct32b 1) - 0.08 0.08 0.04 0.04 gpio0 - 0.34 0.34 0.17 0.17 gpio1 - 0.34 0.34 0.17 0.17 gpio2 - 0.36 0.37 0.18 0.18 i2c - 0.09 0.09 0.05 0.05 iocon - 0.09 0.10 0.05 0.05 rtc - 0.10 0.10 0.05 0.05 ssp - 0.30 0.29 0.15 0.15 uart0 - 0.52 0.51 0.26 0.26 uart1 - 0.52 0.51 0.26 0.26 dma - 0.18 0.18 0.09 0.09 wwdt - 0.06 0.06 0.03 0.03
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 35 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register; all peripheral clocks disabled; internal pull-up resistors dis abled; bod disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. (3) system oscillator enabled; irc and system pll disabled. fig 6. active mode: typical supply current i dd versus supply voltage v dd(3v3) for different system clock frequencie s (all peripher als disabled) conditions: v dd(3v3) = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register; all peripheral clocks disabled; internal pull-up resistors dis abled; bod disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. (3) system oscillator enabled; irc and system pll disabled. fig 7. active mode: typical supply current i dd versus temperature for different system clock frequencies (peripherals disabled) v dd(3v3) (v) 3 3.6 3.4 3.2 002aag186 8 4 12 16 i dd (ma) 0 33 mhz (2) 24 mhz (2) 12 mhz (1) 4 mhz (3) 1 mhz (3) 12 mhz (1) 4 mhz (3) 1 mhz (3) 33 mhz (2) 24 mhz (2) 002aag023 temperature (c) -40 85 35 10 60 -15 4 12 8 16 i dd (ma) 0
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 36 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals enabled in the sysahbclkctrl register. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. (3) system oscillator enabled with external clock input; irc and system pll disabled. fig 8. active mode: typical supply current i dd versus supply voltage v dd(3v3) for different system clock frequenc ies (all peripherals enabled) conditions: v dd(3v3) = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals enabled in the sysahbclkctrl register. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. (3) system oscillator enabled with external clock input; irc and system pll disabled. fig 9. active mode: typical supply current i dd versus temperature for different system clock frequencies (peripherals enabled) v dd(3v3) (v) 3 3.6 3.4 3.2 002aag187 8 4 12 16 i dd (ma) 0 33 mhz (2) 24 mhz (2) 12 mhz (1) 4 mhz (3) 1 mhz (3) 12 mhz (1) 4 mhz (3) 1 mhz (3) 33 mhz (2) 24 mhz (2) 002aag024 temperature (c) -40 85 35 10 60 -15 4 12 8 16 i dd (ma) 0
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 37 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller conditions: v dd(3v3) = 3.3 v; sleep mode entered from flash; all peripherals disabled in the sysahbclkctrl register (sysahbclk ctrl = 0x1f); all peripheral clocks disabled; internal pull-up resistors dis abled; bod disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. (3) system oscillator enabled with external clock input; irc and system pll disabled. fig 10. sleep mode: typical supply current i dd versus supply voltage v dd(3v3) for different system clock frequencies conditions: bod disabled; all oscillators and analog blocks disabled in the pdsleepcfg register fig 11. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd(3v3) v dd(3v3) (v) 3.0 3.6 3.4 3.2 002aag188 2 3 1 4 5 i dd (ma) 0 33 mhz (2) 24 mhz (2) 12 mhz (1) 1 mhz (3) 4 mhz (3) 002aag190 20 40 30 50 i dd (a) 10 temperature (c) -40 85 35 10 60 -15 v dd(3v3) = 3.6 v 3.3 v 3.0 v
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 38 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 10.3 electrical pi n characteristics fig 12. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd(3v3) 002aag189 0.7 0.9 0.8 1.0 i dd (a) 0.6 temperature (c) -40 85 35 10 60 -15 v dd(3v3) = 3.6 v 3.3 v 3.0 v conditions: v dd(io) = 3.3 v fig 13. high-drive pins: typical high-level output voltage v oh versus high-level output current i oh i oh (ma) 0 48 32 16 002aag175 2.8 2.4 3.2 3.6 v oh (v) 2 low mode -40 c +25 c +70 c +85 c low mode -40 c +25 c +70 c +85 c
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 39 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller conditions: v dd(io) = 3.3 v fig 14. high-drive pins: typical low-level output voltage v ol versus low-level output current i ol conditions: v dd(io) = 3.3 v. fig 15. i 2 c-bus pins (high current sink): typical low-level output voltage v ol versus low-level output current i ol i ol (ma) 0 48 32 16 002aag310 0.4 0.8 1.2 v ol (v) 0 low mode -40 c +25 c +70 c +85 c high mode -40 c +25 c +70 c +85 c i ol (ma) 0 48 36 24 12 002aag180 0.4 0.2 0.6 0.8 v ol (v) 0 -40 c +25 c +70 c +85 c
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 40 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller conditions: v dd(io) = 3.3 v. fig 16. normal-drive pins: typical low-level output voltage v ol versus low-level output current i ol conditions: v dd(io) = 3.3 v. fig 17. normal-drive pins: typical high-level output voltage v oh versus high-level output source current i oh 002aag181 i ol (ma) 0 16 12 8 4 0.4 0.8 1.2 v ol (v) 0 - 40 c +25 c +70 c +85 c - 40 c +25 c +70 c +85 c low mode high mode i oh (ma) 0 16 12 8 4 002aag182 2.6 2.2 3.0 3.4 v oh (v) 1.8 -40 c +25 c +70 c +85 c -40 c +25 c +70 c +85 c low mode high mode
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 41 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller conditions: v dd(io) = 3.3 v. fig 18. typical pull-up current i pu versus input voltage v i v i (ma) 0 3 2 1 002aag185 -60 -40 -80 -20 0 i pu (ma) -100 +85 c +70 c +25 c -40 c
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 42 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 10.4 adc characteristics [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] conditions: v ss =0v, v dd(3v3) =3.3v. [3] the adc is monotonic, there are no missing codes. [4] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 19 . [5] the integral non-linearity (e l(adj) ) is the peak difference between the c enter of the steps of the actual and the ideal transfer curve after appropriate adj ustment of gain and offset errors. see figure 19 . [6] the offset error (e o ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. see figure 19 . [7] the gain error (e g ) is the relative difference in percent betw een the straight line fitting the actual transfer curve after removing offset error, and the strai ght line which fits the ideal transfer curve. see figure 19 . [8] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 19 . [9] t amb = 25 ? c; maximum sampling frequency f s = 257 khz and analog input capacitance c ia = 1 pf. [10] input resistance r i depends on the sampling frequency fs: r i = 1 / (f s ? c ia ). table 9. adc static characteristics t amb = ? 40 ? c to +85 ? c unless otherwise specified; adc frequency 9 mhz, v dd(3v3) = 3.0 v to 3.6 v. symbol parameter conditions min typ [1] max unit v ia analog input voltage 0 - v dd(3v3) v c ia analog input capacitance - - 1 pf e d differential linearity error [2] [3] [4] -- ? 1lsb e l(adj) integral non-linearity [2] [5] -- ? 2.5 lsb e o offset error [2] [6] -- ? 1lsb e g gain error [2] [7] -- ? 3lsb e t absolute error [2] [8] -- ? 3lsb f c(adc) adc conversion frequency - - 257 khz r i input resistance [9] [10] -- 3.9 m ?
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 43 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 19. adc characteristics 002aae787 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dd(3v3) ? v ss 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 44 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 10.5 bod static characteristics [1] interrupt levels are selected by writing the level value to the bod control register bodctrl, see lpc122x user manual . table 10. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 1 assertion - 2.25 - v de-assertion - 2.39 - v interrupt level 2 assertion - 2.54 - v de-assertion - 2.67 - v interrupt level 3 assertion - 2.83 - v de-assertion - 2.93 - v reset level 1 assertion - 2.04 - v de-assertion - 2.18 - v reset level 2 assertion - 2.34 - v de-assertion - 2.47 - v reset level 3 assertion - 2.62 - v de-assertion - 2.76 - v
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 45 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 11. dynamic characteristics 11.1 power-up ramp conditions [1] see figure 20 . [2] the wait time specifies the time the power supply must be at levels below 400 mv before ramping up. table 11. power-up characteristics t amb = ? 40 ? c to +85 ?c. symbol parameter conditions min typ max unit t r rise time at t = t 1 : 0 < v i ?? 400 mv [1] 0- 500 ms t wait wait time [1] [2] 12 - - ? s v i input voltage at t = t 1 on pin v dd 0 - 400 mv condition: 0 < v i ?? 400 mv at start of power-up (t = t 1 ) fig 20. power-up ramp v dd 0 400 mv t r t wait t = t 1 002aag001
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 46 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 11.2 flash memory [1] erase and programming times are valid over the lifetime of the device (minimum 20000 cycles). [2] number of program/erase cycles. 11.3 external clock [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 12. dynamic characteristic: flash memory t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. symbol parameter conditions min max unit t er erase time for one page (512 byte) [1] -2 0ms for one sector (4 kb) [1] 162 ms for all sectors; mass erase [1] -2 0ms t prog programming time one word (4 bytes) [1] -4 9 ? s four sequential words [1] -1 94 ? s 128 bytes (one row of 32 words) [1] -7 65 ? s n endu endurance [2] 20000 - cycles t ret retention time 10 - years table 13. dynamic characteristic: external clock t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4--ns t clcx clock low time t cy(clk) ? 0.4--ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns fig 21. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 47 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 11.4 internal oscillators [1] parameters are valid over operating te mperature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at nom inal supply voltages. [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +85 ? c) is ? 40 %. [3] see the lpc122x user manual . table 14. dynamic characteristic: internal oscillators t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz fig 22. internal rc oscillator frequency versus temperature table 15. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -7.8 - khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 1700 - khz 002aag020 11.95 12.05 12.15 f osc(rc) (mhz) 11.85 temperature ( c) ?40 85 35 10 60 ?15 vdd = 3.6 v 3.3 v 3.0 v 12 mhz + 1% 12 mhz ? 1%
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 48 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 11.5 i 2 c-bus [1] parameters are valid over operating tem perature range unless otherwise specified. [2] thd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowl edge. [3] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [4] c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall times are allowed. [5] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection re sistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [6] in fast-mode plus, fall time is specified the same for bot h output stage and bus timing. if se ries resistors are used, desig ners should allow for this when c onsidering bus timing. [7] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time. this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [8] tsu;dat is the data set-up time that is measured with respec t to the rising edge of scl; applies to data in transmission and the acknowledge. [9] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stre tch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. al so the acknowledge timing must meet this set-up time. table 16. dynamic characteristic: i 2 c-bus pins t amb = ? 40 ? c to +85 ? c. [1] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [3] [4] [5] [6] of both sda and scl signals standard-mode -3 0 0n s fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [2] [3] [7] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [8] [9] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 49 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller fig 23. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 50 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 12. application information 12.1 xtal input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. 12.2 xtal printed circuit boar d (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 ,c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. fig 24. slave mode operation of the on-chip oscillator lpc1xxx xtalin c i 100 pf c g 002aae788
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 51 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 12.3 electromagnetic co mpatibility (emc) radiated emission measurements according to the iec61967-2 standard using the tem-cell method are shown for the lpc1227fbd64/301 in ta b l e 1 7 . [1] iec levels refer to appendix d in the iec61967-2 specification . table 17. electromagnetic compatibility (e mc) for part lpc1227fbd64/301 (tem-cell method) v dd = 3.3 v; t amb = 25 ? c. parameter frequency band system clock = unit 12 mhz 24 mhz 33 mhz input clock: irc (12 mhz) maximum peak level 150 khz - 30 mhz ? 4.2 ? 3.8 ? 6.4 db ? v 30 mhz - 150 mhz 7.3 5.4 9 db ? v 150 mhz - 1 ghz 16.4 20.1 23.4 db ? v iec level [1] - mll- input clock: crystal oscillator (12 mhz) maximum peak level 150 khz - 30 mhz ? 4.8 ? 4 ? 6.6 db ? v 30 mhz - 150 mhz 6.9 5.6 10 db ? v 150 mhz - 1 ghz 16.3 20.3 22.3 db ? v iec level [1] - mll-
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 52 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 13. package outline fig 25. package outline sot314-2 (lqfp64) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1)(1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 53 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller fig 26. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1)(1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 54 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 14. soldering fig 27. reflow soldering of the lqfp48 package sot313-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp48 package ax bx gx gy hy hx ayby p1 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 10.350 p2 0.560 10.350 7.350 7.350 p1 0.500 0.280 c 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout p2
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 55 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller fig 28. reflow soldering of the lqfp64 package sot314-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp64 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 13.300 13.300 10.300 10.300 p1 0.500 p2 0.560 0.280 c 1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 56 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 15. abbreviations table 18. abbreviations acronym description adc analog-to-digital-converter ahb advanced high-performance bus apb advanced peripheral bus bod brownout detection ccitt comit consultatif international tlphonique et tlgraphique crc cyclic redundancy check dma direct memory access fifo first-in-first-out gpio general purpose input/output i/o input/output irda infrared data association irc internal resistor-capacitor jedec joint electron devices engineering council pll phase-locked loop spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port uart universal asynchronous receiver/transmitter
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 57 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 16. revision history table 19. revision history document id release date data sheet status change notice supersedes lpc122x v.2 20110826 product data sheet - lpc122x v.1.2 modifications: ? power consumption data updated in table 7 . ? power consumption graphs added in section 10.2 . ? electrical pin characteristics updated for all pins in table 7 and section 10.3 . ? parameter r i added to table 9 . ? emc data added ( section 12.3 ). ? parameter v i updated for i 2 c-bus pins in table 5 . ? section 11.1 ? power-up ramp conditions ? added. ? data sheet status updated to product data sheet. ? ssp dynamic characteristics removed. lpc122x v.1.2 20110329 objective data sheet - lpc122x v.1.1 modifications: ? figure 2 ?pin configuration lqfp64 pack age?: pin rtcxin changed to 58 and pin rtcxout changed to 57. ? table 3 ?lpc122x pin description?: in column pin lqfp64, pin rtcxin changed to 58 and pin rtcxout changed to 57. lpc122x v.1.1 20110221 objective data sheet - lpc122x v.1 modifications: ? section 1 ?general description?: updated text. ? section 2 ?features and benefits?: updated text. lpc122x v.1 20110214 objective data sheet - -
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 58 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 59 of 61 nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc122x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 26 august 2011 60 of 61 continued >> nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 functional description . . . . . . . . . . . . . . . . . . 16 7.1 arm cortex-m0 processor . . . . . . . . . . . . . . . 16 7.1.1 system tick timer . . . . . . . . . . . . . . . . . . . . . . 16 7.2 on-chip flash program memo ry . . . . . . . . . . . 16 7.3 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5 nested vectored interrupt controller (nvic) . 17 7.5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 18 7.6 ioconfig block . . . . . . . . . . . . . . . . . . . . . . 18 7.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.7 micro dma controller . . . . . . . . . . . . . . . . . . . 18 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.8 crc engine . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.9 fast general purpose parallel i/o . . . . . . . . . . 19 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.10 uarts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.11 ssp/spi serial i/o controller . . . . . . . . . . . . . 20 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 20 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.13 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14 comparator block . . . . . . . . . . . . . . . . . . . . . . 21 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.15 general purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16 windowed watchdog timer (wwdt) . . . . . . . 22 7.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.17 real-time clock (rtc) . . . . . . . . . . . . . . . . . . 23 7.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.18 clocking and power control . . . . . . . . . . . . . . 23 7.18.1 crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 23 7.18.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 24 7.18.1.2 system oscillator . . . . . . . . . . . . . . . . . . . . . . 24 7.18.1.3 watchdog oscillator . . . . . . . . . . . . . . . . . . . . 25 7.18.2 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.18.3 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.18.4 wake-up process . . . . . . . . . . . . . . . . . . . . . . 25 7.18.5 power control . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.18.5.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.18.5.2 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 26 7.18.5.3 deep power-down mode . . . . . . . . . . . . . . . . 26 7.19 system control . . . . . . . . . . . . . . . . . . . . . . . . 26 7.19.1 start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.19.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.19.3 brownout detection . . . . . . . . . . . . . . . . . . . . 27 7.19.4 code security (code read protection - crp) 27 7.19.5 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.19.6 ahb-lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.19.7 external interr upt inputs . . . . . . . . . . . . . . . . . 27 7.20 emulation and debugging . . . . . . . . . . . . . . . 28 7.21 integer division routines . . . . . . . . . . . . . . . . . 28 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29 9 thermal characteristics . . . . . . . . . . . . . . . . . 30 9.1 thermal characteristics . . . . . . . . . . . . . . . . . 30 10 static characteristics . . . . . . . . . . . . . . . . . . . 31 10.1 peripheral power consumption . . . . . . . . . . . 34 10.2 power consumption . . . . . . . . . . . . . . . . . . . 34 10.3 electrical pin characteristics. . . . . . . . . . . . . . 38 10.4 adc characteristics . . . . . . . . . . . . . . . . . . . . 42 10.5 bod static characteristics . . . . . . . . . . . . . . . 44 11 dynamic characteristics. . . . . . . . . . . . . . . . . 45 11.1 power-up ramp conditions . . . . . . . . . . . . . . . 45 11.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . 45 11.3 external clock. . . . . . . . . . . . . . . . . . . . . . . . . 46 11.4 internal oscillators . . . . . . . . . . . . . . . . . . . . . 47 11.5 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12 application information . . . . . . . . . . . . . . . . . 50 12.1 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.2 xtal printed circuit board (pcb) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3 electromagnetic compatibility (emc) . . . . . . 51 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 52 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 56 16 revision history . . . . . . . . . . . . . . . . . . . . . . . 57 17 legal information . . . . . . . . . . . . . . . . . . . . . . 58 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 58 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 58
nxp semiconductors lpc122x 32-bit arm cortex-m0 microcontroller ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 26 august 2011 document identifier: lpc122x please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 59 18 contact information. . . . . . . . . . . . . . . . . . . . . 59 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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